I have been developing some tools at work to generated Verilog macros to automate some aspects of an ASIC design implemented in Verilog. Some of these macros can get quite nested and complex and hard to debug at times. That’s what prompted me to look for a Verilog preprocessor that can just evaluate the macros (`defines, `ifdefs, etc.). It didn’t take me long to find Verilog::Preproc which is part of Verilog-Perl (or vppreproc). It is a nifty little Perl utility that is very simple to install and use, and can handle macros defined in Verilog 2001 and SystemVerilog 2005 standards.
