Testbench for ALU 01 design example is shown below.
// ALU 01 port list
// Inputs A, B of 8 bits (operands)
// Output Y of 8 bits (output)
// Input C of 2 bits (control)
// Input clock, input reset
// Testbench
module alu_01_tb_01;
// Declare the wires
logic clk;
logic rst;
logic [7:0] a, b, y;
logic [1:0] c;
// instantiate the device-under-test
alu dut (
.clock (clk),
.reset (rst),
.a (a),
.b (b),
.c (c),
.y (y)
);
// Reset controller
initial begin
reset = 1'b1;
#100;
reset = 1'b0;
end
// Clock generator
always @(*) begin
if (reset) begin
clk = 1'b0;
end else begin
clk = ~clk;
#10;
end
end
// Input stimulus
initial begin
end
endmodule
