Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language. It is aimed a enabling highly parameterizable hardware design using the power of Scala.
From the Chisel website:
Chisel is a library of special class definitions, predefined objects, and usage conventions within Scala, so when you write Chisel you are actually writing a Scala program that constructs a hardware graph.
So why Chisel while we have HDLs like VHDL, Verilog/SystemVerilog?
Here is a quick summary, with more to come.
Languages VHDL and Verilog were initially developed as hardware simulation languages. They were later adapted to support synthesizable hardware descriptions. Many of the constructs in these languages are not synthesizable. While they support some level of parameterization, it is often inadequate to create highly reusable RTL descriptions with parameterization. They also lack object-oriented features that are synthesizable.
Watch this space for a discussion on Chisel.
