Category: SystemVerilog
Verilog/SystemVerilog: Why use structs?
“Why do we need structs when we can represent all…
Design Example: CPU Registers 01
A module that implements registers in a CPU. There are…
SystemVerilog: `define gotchas
It is very common to use macros using `define in…
Design Example: ALU 01 Testbench (alu_01_tb_01)
Testbench for ALU 01 design example is shown below.
SystemVerilog: Source Order Execution
Here is a rule in SystemVerilog (SV) LRM that specifies…
