SystemVerilog: `define gotchas
It is very common to use macros using `define in Verilog and SystemVerilog. While this may be an easy way to define some commonly used…
Chisel: A Language for Software Defined Hardware
Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language. It is aimed a enabling highly parameterizable hardware design using the power…
Design Example: ALU 01 Testbench (alu_01_tb_01)
Testbench for ALU 01 design example is shown below.
SystemVerilog: Source Order Execution
Here is a rule in SystemVerilog (SV) LRM that specifies how non-blocking statements in a begin-end block are executed. Consider the example shown below. It…
Design-Reuse, Portable Design, Retargetable Design, IP
Design reuse is not a new concept. This is something that the software folks have been doing very effectively for decades. Naturally, it makes a…
Verilog::Preproc – The Handy Verilog Preprocessor
I have been developing some tools at work to generated Verilog macros to automate some aspects of an ASIC design implemented in Verilog. Some of…