Recent Posts

Posted in Design Automation Methodology Reusable Designs SystemVerilog

Building the Machine that Builds the Machine: Escaping the RTL Trap with Software Abstraction

TL;DR: Faced with an impossible directive—scaling a complex RTL sub-system into a reusable IP for five concurrent ASICs with a team of only eight designers—we…

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Posted in Design Automation

RTL Is Not Silicon: Deconstructing the “Working Chip in 10 Minutes” Fallacy

A marketing post recently made the rounds on LinkedIn from a hardware design automation startup, complete with the kind of headline guaranteed to trigger an…

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Posted in Semiconductors

Control, Switch, Break: Decoding NPN Transistor Operating Modes

The humble NPN bipolar junction transistor is a semiconductor giant, the heart of modern electronics. Often simplified as a voltage-controlled switch, its power truly lies…

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Posted in Semiconductors

Basic Electronics: Understanding Simple Diode Operation

If you’re delving into electronics, one of the most fundamental semiconductor components you’ll encounter is the diode. Think of a diode as a one-way street…

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Posted in EE-General Home-Improvement

The 38V Ghost in the Machine: Diagnosing a High-Resistance Failure in a 40-Year-Old Panel

The Symptom: The “Half-Dead” Kitchen It started with a common household annoyance: the garbage disposal went silent, but the dishwasher was functional. But as any…

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Posted in SystemRDL

The Source of Truth: Why SystemRDL is the Backbone of Modern SoC Design

TL;DR: The Register Synchronization Abstract In modern SoC design, the Address Map is the “Handshake” between Hardware and Software. Historically, this was managed via error-prone…

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Posted in Design Automation SystemVerilog Verilog

From Paperclips to AI: The Grand Evolution of Chip Design

A deep dive into the history of silicon. How we stopped ‘drawing’ chips with X-Acto knives and started ‘teaching’ them to build themselves using Hardware Description Languages and AI.

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Posted in EE-General

The Red Herring in the Machine: How Expectations Can Sabotage System Testing

In my 18 years of blogging at The Technic Alley, I’ve shared countless technical fixes. But recently, while testing a new chip our team developed,…

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Posted in Design Example SystemVerilog Verilog

Verilog/SystemVerilog: Why use structs?

“Why do we need structs when we can represent all our ports and internal signals with wires, registers, and logic type?” This is one of…

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Posted in Design Example SystemVerilog Verilog

Design Example: CPU Registers 01

A module that implements registers in a CPU. There are 8 registers R0 – R7. Each register is 32-bits wide. Each register has an input…

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