Recent Posts
The Source of Truth: Why SystemRDL is the Backbone of Modern SoC Design
TL;DR: The Register Synchronization Abstract In modern SoC design, the Address Map is the “Handshake” between Hardware and Software. Historically, this was managed via error-prone…
From Paperclips to AI: The Grand Evolution of Chip Design
A deep dive into the history of silicon. How we stopped ‘drawing’ chips with X-Acto knives and started ‘teaching’ them to build themselves using Hardware Description Languages and AI.
The Red Herring in the Machine: How Expectations Can Sabotage System Testing
In my 18 years of blogging at The Technic Alley, I’ve shared countless technical fixes. But recently, while testing a new chip our team developed,…
Verilog/SystemVerilog: Why use structs?
“Why do we need structs when we can represent all our ports and internal signals with wires, registers, and logic type?” This is one of…
Design Example: CPU Registers 01
A module that implements registers in a CPU. There are 8 registers R0 – R7. Each register is 32-bits wide. Each register has an input…
SystemVerilog: `define gotchas
It is very common to use macros using `define in Verilog and SystemVerilog. While this may be an easy way to define some commonly used…
Chisel: A Language for Software Defined Hardware
Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language. It is aimed a enabling highly parameterizable hardware design using the power…
Design Example: ALU 01 Testbench (alu_01_tb_01)
Testbench for ALU 01 design example is shown below.