Category: Verilog
Verilog/SystemVerilog: Why use structs?
“Why do we need structs when we can represent all our ports and internal signals with wires, registers, and logic type?” This is one of…
Design Example: CPU Registers 01
A module that implements registers in a CPU. There are 8 registers R0 – R7. Each register is 32-bits wide. Each register has an input…
SystemVerilog: `define gotchas
It is very common to use macros using `define in Verilog and SystemVerilog. While this may be an easy way to define some commonly used…
Design Example: ALU 01 Testbench (alu_01_tb_01)
Testbench for ALU 01 design example is shown below.
SystemVerilog: Source Order Execution
Here is a rule in SystemVerilog (SV) LRM that specifies how non-blocking statements in a begin-end block are executed. Consider the example shown below. It…
Verilog::Preproc – The Handy Verilog Preprocessor
I have been developing some tools at work to generated Verilog macros to automate some aspects of an ASIC design implemented in Verilog. Some of…