Category: Design Automation
Building the Machine that Builds the Machine: Escaping the RTL Trap with Software Abstraction
TL;DR: Faced with an impossible directive—scaling a complex RTL sub-system into a reusable IP for five concurrent ASICs with a team of only eight designers—we…
RTL Is Not Silicon: Deconstructing the “Working Chip in 10 Minutes” Fallacy
A marketing post recently made the rounds on LinkedIn from a hardware design automation startup, complete with the kind of headline guaranteed to trigger an…
From Paperclips to AI: The Grand Evolution of Chip Design
A deep dive into the history of silicon. How we stopped ‘drawing’ chips with X-Acto knives and started ‘teaching’ them to build themselves using Hardware Description Languages and AI.
Design-Reuse, Portable Design, Retargetable Design, IP
Design reuse is not a new concept. This is something that the software folks have been doing very effectively for decades. Naturally, it makes a…
Verilog::Preproc – The Handy Verilog Preprocessor
I have been developing some tools at work to generated Verilog macros to automate some aspects of an ASIC design implemented in Verilog. Some of…