Tag: Verilog
Verilog/SystemVerilog: Why use structs?
“Why do we need structs when we can represent all our ports and internal signals with wires, registers, and logic type?” This is one of…
SystemVerilog: Source Order Execution
Here is a rule in SystemVerilog (SV) LRM that specifies how non-blocking statements in a begin-end block are executed. Consider the example shown below. It…
Verilog::Preproc – The Handy Verilog Preprocessor
I have been developing some tools at work to generated Verilog macros to automate some aspects of an ASIC design implemented in Verilog. Some of…