Are FPGAs Ready To Tip ASICs?

This is a question that has been asked many times.  A recent statement by Moshe Gavrielov, president and CEO of programmable logic supplier Xilinx Inc., that I read in an EE Times article  caught my attention.  He says “Market and technology forces have finally aligned to create a tipping point whereby field programmable gate arrays (FPGAs) are displacing traditional application specific integrated circuits (ASICs) for many applications.”

Haven’t Xilinx and Altera been saying that for years? Yes, (quoting the article)

But Gavrielov argues that a combination of market forces, economic factors and technological innovations made by programmable devices in recent times have given this argument new weight.

Gavrielov isn’t predicted doomsday for ASICs. But he does make the case that ASICs are being relegated to specialized, high-volume applications and being displaced in most other areas by FPGAs. He maintains that what he calls the “programmable imperative” is being mandated by business conditions, chiefly the growing non-reoccurring engineering investment required to support traditional ASICs.

It is true that the cost of designing and building ASICs is growing rapidly with newer technology nodes like 65nm, 45nm and beyond. Also, typical ASICs being built with these technologies are getting very complex. As a result, it takes a long time to completely specify, design, verify and manufacture these chips. This often becomes the critical path in product development for many applications. So there are many companies that have taken the FPGA route to ship their new products, with a roadmap to either convert them to lower-cost ASICs or design equivalent ASICs in the next phase. While this may work well for many technologies and applications, there are some where the cutting-edge performance that can be achieved only by a making a highly optimized ASIC is essential for the products to succeed. This is what Gavrielov refers to as the “specialized, high-volume applications.” A factor that becomes prohibitive with FPGAs is the cost, but for lower volume products, the saving in ASIC NRE cost works in favor of the FPGAs. What works well with the FPGAs is the the quick turnaround: it is usually much faster to churn an FPGA design and ship a product with it; this also gives you the flexibility to upgrade your designs by shipping new FPGA “programming” code your products after they have been deployed in the field. So if you are designing a product with a brand new standard or one that is still being hashed out, you can come up with an early version and capture some of the market, and upgrade your products in the field when the standards are finalized.

While ASICs will continue to be the best option for highly specialized and high performance applications, and for well-tested large volume “merchant silicon” products, FPGAs will continue to emerge as more and more viable options for less specialized and lower volume applications.