Author: editor
Design-Reuse, Portable Design, Retargetable Design, IP
Design reuse is not a new concept. This is something that the software folks have been doing very effectively for decades. Naturally, it makes a…
Verilog::Preproc – The Handy Verilog Preprocessor
I have been developing some tools at work to generated Verilog macros to automate some aspects of an ASIC design implemented in Verilog. Some of…
Posted in EE-General
EE and Hardware Design/Verification
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